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march 2014 altera corporation ds-1044 datasheet ? 2014 altera corporation. all rights rese rved. altera, arria, cyclone, enpiri on, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera cor poration and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademar ks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current spec ifications in accordance with altera's standard warranty, but reserves the right to make cha nges to any products and services at any time without notice. alt era assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein exce pt as expressly agreed to in writing by altera. altera customers are advised to obtain th e latest version of device specifications before relying on a ny published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered enpirion ? power datasheet ES1010SI 12v hot-swap power distribution controllers the altera? enpirion? ES1010SI is a fully featured hot-swap power controller that target s +12v applications. the ES1010SI has an integrated char ge pump, which can generate a higher (6.5v) gate drive to improve efficiency. this ic features programmable overcurrent (oc) detection, current regulation (cr) with time delay to latch-off and soft- start. the current regulation level is set by 2 external resistors; r iset- sets the cr vth and the other is a low ohmic sense resistor across, which the cr vth is developed. the cr duration is set by an external capacitor on the cltim pin, which is charged with a 20a cu rrent once the cr vth level is reached. the ic then quickly pulls down the gate output latching off the pass fet. features ? hot-swap single power distribution control for +12v ? overcurrent fault isolation ? programmable current regulation level ? programmable current regul ation time to latch-off ? rail-to-rail common mode input voltage range ? enhanced internal charge pump drives n-channel mosfet gate to 6.5v above ic bias. ? undervoltage and overcu rrent latch indicators ? adjustable turn-on ramp ? protection during turn-on ? two levels of overcurrent detection provide fast response to varying fault conditions ? 1s response time to dead short ? pb-free (rohs compliant) applications ? fpga, dsp, and asic power protection ? power distribution control ? hot plug components and circuitry application circuits - high side controller +12v - + en load pok oc 1 2 3 4 8 7 6 5 ES1010SI +v supply to be controlled 09617 march 14, 2014 rev a
page 2 ES1010SI 12v hot-swap power distribution controllers marc h 2014 altera corporation ordering information pin configuration ES1010SI (8 ld soic) top view part number (notes 1, 3) part marking temperature range (c) package (pb-free) pkg. dwg. # ES1010SI 1010 -40 to +85 8 ld soic m8.15 evb-ES1010SI evaluation platform notes: 1. these altera enpirion pb-free plastic p ackaged products employ speci al pb-free material sets, molding compounds/die attach ma terials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations). altera enpirion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb -free requirements of ipc/jedec j std-020.. pin descriptions pin no. symbol function description 1 iset- current set connect to the low side of the current se nse resistor through the current limiting set resistor. this pin functions as the current limit programming pin. 2 isen+ current sense connect to the more pos itive end of sense resistor to measur e the voltage drop across this resistor. 3 gate external fet gate drive pin connect to the gate of the ex ternal n-channel mosfet. a capac itor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to v in +6.5v by an 14a current source. 4 gnd chip return 5 vin chip supply 12v chip supply. this can be either connected directly to the +12v rail supplying the switched load voltage or to a dedicated gnd +12v supply. 6 cltim current limit timing capacitor connect a capacitor from this pin to ground. this capacitor dete rmines the time delay between an overcurrent event and chip output shutdown (current limit time-out). the duration of current limit time-out is equal to 93k ? x cltim. 7 pok power good indicator indicates that the voltage on the isen+ pin is satisfactory. pok is driven by an open drain n-channel mosfet and is pulled low when the ou tput voltage (visen+) is less than the uv level for the particular ic. 8 en power-on en is used to control and reset the chip. the chip is enabled when en pin is driven high to a maximum of 5v or is left open. do not drive th is input >5v. after a cu rrent limit tim e-out, the chip is reset by a low level signal applied to this pin. this input has 20a pull-up capability. iset- isen+ gate gnd 1 2 3 4 8 7 6 5 en pok cltim vin 09617 march 14, 2014 rev a
page 3 ES1010SI 12v hot-swap po wer distribution controllers march 2014 altera corporation absolute maximum ratings t a = +25 c thermal information v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +16v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to v in + 8v isen+, pok, en, cltim, iset- . . . . . . . . . . . -0.3v to v in + 0.3v operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . +12v 15% temperature range ( t a ) . . . . . . . . . . . . . . . . . . . . . . -40c to +85c esd human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kv machine model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250v thermal resistance (typical, note 2) ? ja (c/w) 8 ld soic package . . . . . . . . . . . . . . . . . . . . . . 98 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? caution: do not operate at or near the ma ximum ratings listed for extended periods of time. exposure to su ch conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. ? ja is measured with the co mponent mounted on a high effective thermal conductivity test board in free air. 3. all voltages are relative to gnd, unless otherwise specified. electrical specifications v in = 12v, t a = t j = full temperature range, unless otherwise specified. parameter symbol test conditions min (note 4) typ max (note 4) units current control iset- current source i iset_ft 17 20 22 a iset- current source i iset_pt t j = +15 c to +55 c 19 20 21 a current limit amp offset voltage vio_ft v iset- - v isen+ -4.5 0 4.5 mv current limit amp offset voltage vio_pt v iset- - v isen+, t j = +15 c to +55 c -2 0 2 mv gate drive gate response time to severe oc pd_woc_amp v gate to 10.8v - 100 - ns gate response time to overcurrent pd_oc_amp v gate to 10.8v - 600 - ns gate turn-on current i gate v gate to = 6v 10.8 14 16.7 a gate pull-down current oc_gate_i_4v overcurrent 45 82 124 ma gate pull-down current (note 4) woc_gate_i_4v severe overcurrent - 0.8 - a undervoltage threshold 12v uv_vth 8.9 9.6 10.2 v gate high voltage 12vg gate voltage v in + 5.7v v in + 6.5v - v bias v in supply current i vin - 3 3.9 ma v in por rising threshold v in_por_l2h v in low to high 7 8.4 9 v v in por falling threshold v in_por_h2l v in high to low 6.9 8.1 8.7 v v in por threshold hysteresis v in_por_hys v in_por_l2h - v in_por_h2l 0.1 0.3 0.5 v maximum en pull-up voltage pwrn_puv maximum exte rnal pull-up voltage - 5 - v 09617 march 14, 2014 rev a
page 4 ES1010SI 12v hot-swap power distribution controllers marc h 2014 altera corporation simplified block diagram description and operation the ES1010SI is targeted for +12v single power supply distribution co ntrol for generic hot swap switching applications. this ics features a highly accurate programmable current regulation (cr) level with programmable time delay to latch-off, and programmable soft-start turn-on ramp all set with a minimum of external passive compon ents. it also includes severe oc protecti on en pull-up voltage v en en pin open 2.5 3.2 - v en rising threshold v en_thr 1.1 1.7 2.35 v en hysteresis en_hys 125 170 250 mv en pull-up current i en 12.6 17 24 a current regulation duration/power good c cltim charging current c cltim _ichg0 v cltim = 0v 17.2 20.5 25 a c cltim fault pull-up current (note 4) -20 - ma current limit time-out threshold voltage c cltim _vth cltim voltage 1.6 1.8 2.1 v power good pull down current pg_ipd v out = 0.5v - 8 - ma notes: 4. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v in = 12v, t a = t j = full temperature range, unless otherwise specified. parameter symbol test conditions min (note 4) typ max (note 4) units + - iset- isen+ gate gnd vin cltim pok en clim woclim enable oc 10a falling edge delay 18v + - v ref + - 1.86v 12v + - r r s qn q enable por v in 8v rising edge pulse + - + - uv 18v 20a 7.5k + - + - 20a uv disable 09617 march 14, 2014 rev a
page 5 ES1010SI 12v hot-swap po wer distribution controllers march 2014 altera corporation that immediately shuts down the mosfet switch should a rapid load curren t transient such as with a dead short cause the cr vth to exceed the programmed level by 150mv. additi onally, it has an uv indicator and an oc latch indicator. the functionality of the pok feature is enabled once the ic is biased, monitoring and reporting any uv condition on the isen+ pin. upon initial power-up, the ic can either isolate the voltage supply from the load by holding the external n-channel mosfet switch off or apply the supply rail voltage directly to the load for true hot swap capability. the en pin must be pulled low for the device to isolate the power supply from the load by holding the external n-channel mosfet off. with the en pin held high or floating the ic will be in true hot swap mode. in both cases the ic turns on in a so ft-start mode protec ting the supply rail fr om sudden inrush current. at turn-on, the external gate capacitor of the n-channel mosfet is charged with a 11a current source resulting in a programmable ramp (soft-start turn-on). the internal ES1010SI charge pump supplies the gate dr ive for the 12v supply switch driving that gate to ~v in +6.5v. load current passes through the external current sense resistor . when the voltage across the sense resistor exceeds the user programmed cr vol tage threshold value, (see table 1 for r iset- programming resistor value and resulting nominal current regulation threshold voltage, v cr ) the controller enters its current regulation mode. at this time, the time-out capacitor, on cltim pin is charged with a 20a current s ource and the controller ente rs the current limit time to latch-off period. the length of the current limit time to latch- off duration is set by the value of a single external capacitor (see table 2) for c cltim capacitor value and resulting nominal current limited t ime-out to latch-off duration placed from the cltim pin (pin 6) to ground. the programmed current level is held until either the oc event passes or the time-out period expires. if the former is the case the n the n- channel mosfet is fully enhanced and the c cltim capacitor is discharged. once c cltim charges to ~1.8v signaling that the time-out period has expired, an internal latch is set whereby the fet ga te is quickly pulled to 0v turn ing off the n-ch annel mosfet swit ch, isolating the faulty load. this ic responds to a severe overcurrent lo ad (defined as a voltage across the sens e resistor >150mv over the oc vth set point) by immediately driving the n-channel mosfet gate to 0v in about 10 s. the gate voltage is then slowly ramped up turning on the n-channel mosfet to the programmed current regulation level; this is the start of the time-out period. upon a uv condition, the pok signal will pull low when connected through a resistor to the logic or vin supply. this pin is a u v fault indicator. for an oc latch-off indicat ion, monitor cltim, pin 6. this pin will rise rapidly from 1.8v to vin once the tim e- out period expires. see figures 2 through 13 for graphs and waveforms related to text. the ic is reset after an oc latch-off condition by a low level on the en pin and is turned on by the en pin being driven high. application considerations design applications where the cr vth is set extremely lo w (25mv or less), there is a two-fold risk to consider. ? there is the susceptibility to noise influencing the absolute cr vth value. this can be addressed with a 100pf capacitor acros s the r sense resistor. ? due to common mode limitations of the overcurrent comparator, the voltage on th e iset- pin must be 20mv above the ic ground either initially (from i set- *r set ) or before c cltim reaches time-out (from gate charge-u p). if this does not happen, the ic may incorrectly report overcurrent fault at start-up when there is no faul t. circuits with high load capacitance and initially low load current are susceptible to th is type of unexpected behavior. do not signal nor pull-up the en input to > 5v. exceeding 6v on this pin will cau se the internal charge pump to malfunction. table 1. r iset- programming resistor value r iset- resistor nominal cr vth 10k ? 200mv 4.99k ? 100mv 2.5k ? 50mv 1.25k ? 25mv note: nominal vth = r iset- x 20a. table 2. c cltim capacitor value c cltim capacitor nominal current limited period 0.022f 2ms 0.047f 4.4ms 0.1f 9.3ms note: nominal time-out period = c cltim x 93k ? . 09617 march 14, 2014 rev a
page 6 ES1010SI 12v hot-swap power distribution controllers marc h 2014 altera corporation during the soft-start and the t ime-out delay duration with the ic in its current limit mode, the v gs of the extern al n-channel mosfet is reduced driving the mosfet sw itch into a (linear region) high r ds(on) state. strike a balance between the cr limit and the timing requirements to avoid periods wh en the external n-channel mosfets may be damaged or destroyed due to excessive internal power dissipation. refer to the mosfet soa information in the manu facturer?s data sheet. when driving particularly large capacitive loads a longer soft-start tim e to prevent current regulation upon charging and a sho rt cr time may offer the best application solution relative to reliability and fet mtf. physical layout of r sense resistor is critical to avoid the possibility of false overcurrent occurrences. ideally, trace routing between the r sense resistors and the ic is as direct and as short as possi ble with zero current in the sense lines (see figure 1). . correct to isen+ and current sense resistor incorrect figure 1. sense resistor pcb layout r iset 09617 march 14, 2014 rev a
page 7 ES1010SI 12v hot-swap po wer distribution controllers march 2014 altera corporation typical performance curves figure 2. v in bias current figure 3. i set- source current figure 4. c cltim current source figure 5. c cltim oc voltage threshold figure 6. uv threshold figure 7. gate charge current 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 -40 0 25 85 125 temperature (c) i dd (ma) 70 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 temperature (c) i set- (a) -40 0 25 85 125 70 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 -40 0 25 70 85 125 temperature (c) cltim charge current (a) cltim - 0v 1.77 1.78 1.79 1.80 1.81 1.82 -40 0 25 70 85 125 temperature (c) c cltim v th (v) 9.60 9.65 9.70 9.75 9.80 -40 0 25 70 85 125 temperature (c) uv th (v) 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 -40 0 25 70 85 125 temperature (c) gate turn-on current (a) 09617 march 14, 2014 rev a
page 8 ES1010SI 12v hot-swap power distribution controllers marc h 2014 altera corporation figure 8. power-on reset voltage threshold figure 9. gate voltage vs bias and temperature figure 10. ES1010SI turn-on figure 11. ES1010SI turn-off typical performance curves (continued) (eq. 1) i dd1 72 12 ? ?? 1.58k ? ----------------------- - = i dd1 38ma typicalvalue 12vrating, 50ma reverse current = ?? = 7.5 7.6 7.7 7.8 7.9 8.0 8.1 8.2 8.3 -40 0 25 70 85 125 temperature (c) power on reset (v) v in lo to hi v in hi to lo 13 14 15 16 17 18 19 20 21 22 9101112131415 bias voltage (v) gate voltage (v) +85c +25c -40c en vout gate pok vout en gate pok vout 09617 march 14, 2014 rev a
page 9 ES1010SI 12v hot-swap po wer distribution controllers march 2014 altera corporation evb-ES1010SI board the evb-ES1010SI is default provided as a + 12v high side switch controller with the cr level set at ~2.5a. see figure 11 for evb-ES1010SI schematic and table 3 for bom. bias and load connection points are provide d along with test points for each ic pin. with j1 installed the ES1010SI will be biased from the +12v supply (v in ) being switched. connect th e load to vload+. en pin pulls high internally enabling the ES1010SI if not driven low via en test point or j2. with r 3 = 1.24k ? the cr vth is set to 24.8mv and with the 10m ? sense resistor (r 1 ) the evb-ES1010SI has a nominal cr level of 2.5~a. the 0.01f delay time to latch-of f capacitor results in a nominal 1ms before latch-off of output after an oc event. reconfiguring the evb-ES1010SI board for a hi gher cr level can be done by changing the r sense and/or r iset- resistor values as the provided fet is rated for a much higher current. figure 12. ioc regulation and turn-off figure 13. woc turn-off and restart figure 14. evb-ES1010SI high side switch application typical performance curves (continued) vout gate iload cltim vout gate iload cltim 5 6 8 7 4 3 2 1 ES1010SI q1 r3 r2 c1 c3 r4 j1 v bias v in +12v c2 r1 en v bias agnd vload+ u1 vout c cltim j2 pok 09617 march 14, 2014 rev a
page 10 ES1010SI 12v hot-swap power distribution controllers marc h 2014 altera corporation document revision history the table lists the revision history for this document. table 3. bill of materials, evb-ES1010SI component designator component name component description u1 ES1010SI altera enpirion q1 n-fet 11.5m ? , 30v, 11.5a logic level n-channel power mosfet or equivalent r1 load current sense resistor wsl-2512 10m ? 1w metal strip resistor r2 gate stability resistor 20 ? 0603 chip resistor r3 overcurrent voltage threshold set resistor 1.24k ? 0603 chip resistor (vth = 24.8mv) r4 pok pull up resistor 10k ? 0603 chip resistor c1 gate timing capacitor 0.001 f 0402 chip capacitor (<2ms) c2 ic decoupling capacitor 0.1 f 0402 chip capacitor c3 time delay set capacitor 0.01 f 0402 chip capacitor (1ms) j1 bias voltage selection jumper install if switched rail voltage is = +12v. j2 en disable install j2 to disable u2. connects en to gnd. date version changes march 2014 1.0 initial release. 09617 march 14, 2014 rev a
page 11 ES1010SI 12v hot-swap po wer distribution controllers march 2014 altera corporation small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of pub- lication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs sh all not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0. 36mm (0.014 inch) or greater above the seating plane, shall not exceed a ma ximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. c onverted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 a 0 8 0 8 - rev. 1 6/05 09617 march 14, 2014 rev a

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